IntelliCAM

REFERENCE CIRCUIT The nominal reference voltage at the REFIN/OUT pin is 2.42 V. This is the reference voltage used for the ADCs in the ADE7758. However, the current channels have three input range selections (full scale is selectable among 0.5 V, 0.25 V, and 0.125 V). This is achieved by dividing the reference internally by 1, ½, and ¼. The reference value is used for the ADC in the current channels. Note that the full-scale selection is only available for the current inputs. The REFIN/OUT pin can be overdriven by an external source, for example, an external 2.5 V reference. Note that the nominal reference value supplied to the ADC is now 2.5 V and not 2.42 V. This has the effect of increasing the nominal analog input signal range by 2.5/2.42 × 100% = 3% or from 0.5 V to 0.5165 V. The voltage of the ADE7758 reference drifts slightly with temperature; see the Specifications section for the temperature coefficient specification (in ppm/°C). The value of the temperature dri

PEAK VOLTAGE DETECTION The ADE7758 can record the peak of the voltage waveform and produce an interrupt if the current exceeds a preset limit. ADE7758은 전압 파형의 피크값을 기록할 수 있으며 전류가 기정의 한계값을 초과하게되면 인터럽트를 발생할 수 있다. Peak Voltage Detection Using the VPEAK Register The peak absolute value of the voltage waveform within a fixed number of half-line cycles is stored in the VPEAK register. Figure 58 illustrates the timing behavior of the peak voltage detection. 반-선형 사이클의 고정수내의 전압 파형의 피크 절대값은 VPEAK 레지스터에 기록된다. 그림58은 피크 전압 검출의 타이밍 상태를 표현한 것이다. Note that the content of the VPEAK register is equivalent to Bit 6 to Bit 13 of the 16-bit voltage waveform sample. At full-scale analog input, the voltage waveform sample at 60 Hz is 0x2748. The VPEAK at full-scale input is therefore expected to be 0x9D. In addition, multiple phases can be activated for the peak detection simultaneously by setting multiple bits among the PEAKSEL[2:4] bits in the MMODE register. These bits select the phas

PHASE COMPENSATION When the HPF in the current channel is disabled, the phase error between the current channel (IA, IB, or IC) and the corresponding voltage channel (VA, VB, or VC) is negligible. When the HPF is enabled, the current channels have phase response (see Figure 53 through Figure 55). The phase response is almost 0 from 45 Hz to 1 kHz. The frequency band is sufficient for the requirements of typical energy measurement applications. However, despite being internally phase compensated, the ADE7758 must work with transducers that may have inherent phase errors. For example, a current transformer (CT) with a phase error of 0.1° to 0.3° is not uncommon. These phase errors can vary from part to part, and they must be corrected to perform accurate power calculations. 전류 채널의 HPF가 비활성화일 때, 전류 채널(IA, IB, IC)와 통신 전압 채널(VA, VB, BC)사이의 상 오차값은 무시할 수 있을 정도로 작다. HPF가 활성상태일 때, 전류 채널은 상 응답을 가진다. 상 응답은 45Hz에서 1kHz까지 대부분 0값이다. 주파수 대역은 전형적인 에너지 측정 응용의 요구 사항에 대해 충분한 값이다. 그러나, 내부적

VOLTAGE CHANNEL ADC Figure 49 shows the ADC and signal processing chain for the input VA in the voltage channel. The VB and VC channels have similar processing chains. For active and reactive energy measurements, the output of the ADC passes to the multipliers directly and is not filtered. This solution avoids the much larger multibit multiplier and does not affect the accuracy of the measurement. An HPF is not implemented on the voltage channel to remove the dc offset because the HPF on the current channel alone should be sufficient to eliminate error due to ADC offsets in the power calculation. However, ADC offset in the voltage channels produces large errors in the voltage rms calculation and affects the accuracy of the apparent energy calculation. 그림49는 ADC와 전압 채널의 입력 VA 에 대한 신호 처리 계열을 보여준다. VB와 VC 채널은 유사한 처리 계열을 가진다. 유효와 무효 에너지 측정에 대해, ADC 의 출력은 필터링되지 않고 직접 승산기로 패스된다. 이 솔루션은 매우 큰 다중비트 승산을 막으며 측정의 정확도에 불리하게 작용하지 않는다. HPF는 전력 계산에서 ADC 옵셋에 상응하는 오차를 업애기에 충분한 단일 전류 채널 상

CURRENT CHANNEL ADC Figure 41 shows the ADC and signal processing path for the input IA of the current channels (same for IB and IC). In waveform sampling mode, the ADC outputs are signed twos complement 24-bit data-words at a maximum of 26.0 kSPS (thousand samples per second). With the specified full-scale analog input signal of ±0.5 V, the ADC produces its maximum output code value (see Figure 41). This diagram shows a full-scale voltage signal being applied to the differential inputs IAP and IAN. The ADC output swings between 0xD7AE14 (−2,642,412) and 0x2851EC (+2,642,412). 그림41은 전류 채널의 IA 입력에 대한 ADC와 신호 처리선을 보여준다. 파형 샘플링 모드에서, ADC 출력값은 26.0kSPS 최대값에서 부호있는 이의 보수 24비트 데이타 워드값이다. 명시된 +-0.5V 최대 축척 아날로그 입력 신호를 가진 ADC 는 최대 출력 코드값을 제공한다. 이 도표는 미분 입력 IAP와 IAN 에서 공급된 최대 축척 전압 신호값을 보여준다. ADC 출력은 0xD7AE14와 0x2851EC 사이값을 가진다. Current Waveform Gain Registers There is a multiplier in the signal path in the current channel for each phase. The current waveform can be changed by ±5

Phase Error Between Channels The high-pass filter (HPF) and digital integrator introduce a slight phase mismatch between the current and the voltage channel. The all-digital design ensures that the phase matching between the current channels and voltage channels in all three phases is within ±0.1° over a range of 45 Hz to 65 Hz and ±0.2° over a range of 40 Hz to 1 kHz. This internal phase mismatch can be combined with the external phase error (from current sensor or component tolerance) and calibrated with the phase calibration registers. HPF와 디지탈 적분자는 전류와 전압 채널 사이에서 약간의 상 오차를 가져온다. 모든 디지탈 설계는 45 Hz ~ 65 Hz ±0.2° 범위에 대해 ±0.1° 오차 범위의 3상 모두에서 전류 채널과 전압채널 사이의 상 일치를 확실히 해야 한다. 이러한 내부 상 불일치는 외부 상 오차값과 결합될 수 있고 상 보정 레지스터에 대해 보상될 수 있다. Power Supply Rejection (PSR) This quantifies the ADE7758 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (5 V) is taken. A second reading is obtained with the sam